In a semiconductor device (power semiconductor module) having a semiconductor circuit that converts an alternating current to a direct current or in a power converter apparatus (inverter apparatus) having a capacitor module that forms a DC smoothing circuit in the power semiconductor module, its interconnection inductance is required to be reduced.
Japanese Laid-Open Patent Publication No. 2005-347561 discloses a structure and a configuration that reduce the inductance in each of the internal wiring of a power semiconductor module, the internal wiring of a capacitor module, and the external wiring from the capacitor module to the semiconductor module. Specifically, as shown in FIGS. 14A and 14B, a plurality of insulated substrates 72 are provided on a base 71. A switching chip 73 and a diode chip 74 are provided on each insulated substrate 72. A P-type conductor (positive conductor) 75 and a N-type conductor (negative conductor) 76 are laminated, while being insulated from each other, on the top surface of each of the switching chip 73 and the diode chip 74. An insulation case (not shown) is arranged over the base 71 to cover the insulated substrates 72, the switching chips 73, the diode chips 74, the P-type conductor (positive conductor) 75, and the N-type conductor (negative conductor) 76. The P-type conductor 75 and the N-type conductor 76 include flat plate-like main conductors 75a, 76a and belt-like sub-conductors 75b, 76b formed at ends of the main conductors 75a, 76a, respectively. The sub-conductor 75b of the P-type conductor 75 and the sub-conductor 76b of the N-type conductors 76 are adjacent to each other while being insulated from each other, and form external terminals P2, N2, respectively. The above described publication also discloses an inverter apparatus in which a capacitor module is located on an insulation case of the a power semiconductor module. The publication further discloses an inverter apparatus having branched conductors each provided on one of the main conductors 75a and 76a of the P-type conductor 75 and the N-type conductor 76. The branched conductors connect the main conductors 75a, 76a to the capacitor element of the capacitor module.
The publication discloses a configuration in which the P-type conductor 75 and the N-type conductor 76 of the power semiconductor module are laminated while being insulated from each other, and the P-type conductor and the N-type conductor of the capacitor module are laminated while being insulated from each other, so that the inductance of the internal wiring of the power semiconductor module and the inductance of the internal wiring of the capacitor module are reduced. The publication also discloses a configuration in which the external terminals P2, N2 are formed at ends of the belt-like sub-conductors 75b, 76b, and the sub-conductors 75b, 76b are located close to and parallel with each other, so that the inductance is reduced.
In a power semiconductor module, when the amount of current through a switching element is great, a plurality of switching element connected in parallel are used instead of using a single switching element in some cases. In this case, in order to reduces the inductance of the entire internal wiring of the power semiconductor module, it is important to consider the relationship between the switching chips 73 and connecting points between circuit patterns on the insulated substrates 72 and connecting conductors 75u, 75v, 75w, 76u, 76v, 76w for supplying currents through the main conductors 75a, 76a to the circuit patterns. However, the above described publication discloses no configuration for reducing the inductance of the entire internal wiring of a power semiconductor module that uses a plurality of switching elements that are connected in parallel instead of using a single switching element.